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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
CLB Switching Characteristics
Table 29: CLB Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.9V
Units
-3
-2/-2L
-1
-1M
-2L
Combinatorial Delays
T ILO
T ILO_2
T ILO_3
T ITO
T AXA
T AXB
T AXC
T AXD
T BXB
T BXD
T CXC
T CXD
T DXD
An – Dn LUT address to A
An – Dn LUT address to AMUX/CMUX
An – Dn LUT address to BMUX_A
An – Dn inputs to A – D Q outputs
AX inputs to AMUX output
AX inputs to BMUX output
AX inputs to CMUX output
AX inputs to DMUX output
BX inputs to BMUX output
BX inputs to DMUX output
CX inputs to CMUX output
CX inputs to DMUX output
DX inputs to DMUX output
0.05
0.15
0.24
0.58
0.38
0.40
0.39
0.43
0.31
0.38
0.27
0.33
0.32
0.05
0.16
0.25
0.61
0.40
0.42
0.41
0.44
0.33
0.39
0.28
0.34
0.33
0.06
0.19
0.30
0.74
0.49
0.52
0.50
0.52
0.40
0.47
0.34
0.41
0.40
0.06
0.19
0.30
0.74
0.49
0.52
0.50
0.52
0.40
0.47
0.34
0.41
0.40
0.07
0.22
0.37
0.91
0.62
0.66
0.62
0.67
0.51
0.62
0.43
0.54
0.52
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
Sequential Delays
T CKO
T SHCKO
Clock to AQ – DQ outputs
Clock to AMUX – DMUX outputs
0.26
0.32
0.27
0.32
0.32
0.39
0.32
0.39
0.40
0.46
ns, Max
ns, Max
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
T AS /T AH
T DICK /T CKDI
T CECK_CLB /
T CKCE_CLB
T SRCK /T CKSR
A N – D N input to CLK on A – D Flip Flops
A X – D X input to CLK on A – D Flip Flops
A X – D X input through MUXs and/or carry
logic to CLK on A – D Flip Flops
CE input to CLK on A – D Flip Flops
SR input to CLK on A – D Flip Flops
0.01/0.12
0.04/0.14
0.36/0.10
0.19/0.05
0.30/0.05
0.02/0.13
0.04/0.14
0.37/0.11
0.20/0.05
0.31/0.07
0.03/0.18
0.05/0.20
0.46/0.16
0.25/0.05
0.37/0.09
0.03/0.24
0.05/0.26
0.46/0.22
0.25/0.11
0.37/0.22
0.02/0.18
0.05/0.21
0.56/0.15
0.24/0.04
0.48/0.05
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Set/Reset
T SRMIN
T RQ
T CEO
F TOG
SR input minimum pulse width
Delay from SR input to AQ – DQ flip-flops
Delay from CE input to AQ – DQ flip-flops
Toggle frequency (for export control)
0.52
0.38
0.34
1818
0.78
0.38
0.35
1818
1.04
0.46
0.43
1818
1.04
0.46
0.43
1818
0.95
0.59
0.54
1286
ns, Min
ns, Max
ns, Max
MHz
DS182 (v2.8) March 4, 2014
Product Specification
30
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